The present invention relates in general to a static random access memory (SRAM), and, more particularly, to an SRAM having improved latch-up characteristics.
RAM chips are well known in the art. An SRAM chip is conventionally structured in rows and columns of individual SRAM cells. A prior art six transistor CMOS SRAM cell 1 is shown schematically in FIG. 1. The SRAM cell 1 includes two n-type access transistors 5, 6, two p-type pull-up transistors 7, 8 acting as load devices, and two n-type pull-down transistors 9, 10, with the pull-transistors 7,8 and pull-down transistors 9, 10 forming two CMOS inverters. The SRAM cell 1 has two states: logic state xe2x80x9c0xe2x80x9d and logic state xe2x80x9c1xe2x80x9d. By convention, if logic state xe2x80x9c0xe2x80x9d is designated by node A having a high voltage and node B having a low voltage, then logic state xe2x80x9c1xe2x80x9d has the opposite stored voltages, i.e., node A having a low voltage and node B having a high voltage.
In logic state xe2x80x9c0xe2x80x9d the high voltage on node A turns on the pull-down transistor 9 and turns off the pull-up transistor 7, whereas the low voltage on node B turns off the pull-down transistor 10 and turns on the pull-up transistor 8. Because the pull-down transistor 9 is on and the pull-up transistor 7 is off, current flows through the pull-down transistor 9 to a voltage supply VSS (ground), thereby maintaining a low voltage on node B. Because the pull-up transistor 8 is turned on and the pull-down transistor 10 is turned off, current flows from a voltage supply VCC through the pull-up transistor 8, thereby maintaining a high voltage on node A.
To change the state of the SRAM cell 1 from a logic xe2x80x9c0xe2x80x9d to a logic xe2x80x9c1xe2x80x9d, a column line 3 and a column line complement 2 are provided with a low and a high voltage, respectively. Then, the access transistors 5 and 6 are turned on by a high voltage on a row line 4, thereby providing the low voltage on the column line 3 to node A and the high voltage on the column line complement 2 to node B. Accordingly, the pull-down transistor 9 is turned off and the pull-up transistor 7 is turned on by the low voltage on node A and the pull-down transistor 10 is turned on and the pull-up transistor 8 is turned off by the high voltage on node B, thereby switching the state of the circuit from logic xe2x80x9c0xe2x80x9d to logic xe2x80x9c1xe2x80x9d. Following the switching of the state of the SRAM cell 1, the access transistors 5 and 6 are turned off (by applying a low voltage on row line 4). The SRAM cell 1 maintains its new logic state in a manner analogous to that described above.
FIGS. 2A and 2B are a schematic diagram and cross-section, respectively, of one of the CMOS inverters of FIG. 1 illustrating parasitic transistors and resistors of the inverter. As shown in FIG. 2B, the pull-down transistor 9 is formed within a P-type substrate 12 while the pull-up transistor 7 is formed within an N-well 14. The N-well 14 is formed within the P-type substrate 12. The N-well 14 includes parasitic resistance denoted by the resistor 16 and the P-type substrate includes parasitic resistance denoted by the resistor 18. The configuration of the pull-down transistor 9 and the pull-up transistor 7 results in the existence of a PNP parasitic bipolar transistor 20 and an NPN parasitic bipolar transistor 22.
With the tight layout spacings that exist in a typical memory array, leakage currents from the N-well 14 and the P-type substrate 12 are possible. These leakage currents produce a voltage drop across the parasitic resistor 16. If the voltage drop becomes sufficiently large, it can result in the parasitic PNP transistor 20 turning on and conducting current from the P+ region forming its emitter to the P-type substrate 12 that forms its collector. The P-type substrate 12 also forms the base terminal of the parasitic NPN transistor 22 and one terminal of the parasitic resistor 18. The other terminal of the parasitic resistor 18 is the substrate tie-down represented by VBB. The current flowing through the resistor 18 produces a voltage rise at the point of injection. If this voltage rise becomes sufficiently large, it can result in the NPN transistor 22 turning on causing additional current to be drawn out the N-well 14 as collector current for the NPN transistor 22. This additional current reinforces the original leakage from the N-well 14 turning the PNP transistor 20 on even harder providing added base current for the NPN transistor 22. This feedback loop can result in a latch-up problem within the memory array containing the SRAM cell.
Accordingly, there is a need for an improved SRAM memory cell that is not prone to latch-up.
The present invention meets this need by providing an SRAM memory cell in which the source of the p-type pull-up transistor is coupled to VCC through the parasitic resistance of the N-well in which it is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.
According to a first aspect of the present invention, an SRAM memory cell is provided comprising a first pull-up transistor having a first substrate, a first source, a first gate coupled to a first node, and a first drain coupled to a second node. The first source is coupled to a first voltage input through parasitic resistance of the first substrate. A first pull-down transistor is provided having a second drain coupled to the second node, a second gate coupled to the first node, and a second source coupled to a second voltage source. An input line is coupled to the first node for providing a signal to the memory cell to change the memory cell from a first logic state to a second logic state. The input line may comprise an access transistor having one terminal coupled to the first node, another terminal coupled to a column line, and an access gate coupled to a row line.
According to another aspect of the present invention, an SRAM memory cell is provided comprising a first pull-up transistor, a first pull down transistor, a second pull-up transistor, a second pull-down transistor, and an input line. The first pull-up transistor includes a first substrate, a first source, a first gate coupled to a first node, and a first drain coupled to a second node. The first pull-down transistor includes a second drain coupled to the second node, a second gate coupled to the first node, and a second source coupled to a second voltage input. The second pull-up transistor includes a second substrate, a third source, a third gate coupled to the second node, and a third drain coupled to the first node. The second pull-down transistor includes a fourth drain coupled to the first node, a fourth gate coupled to the second node, and a fourth source coupled to the second voltage input. The first source is coupled to a first voltage input through parasitic resistance of the first substrate while the third source is coupled to the first voltage input through parasitic resistance of the second substrate. The input line is coupled to the first and second nodes for providing a signal to the memory cell to change the memory cell from a first logic state to a second logic state. Preferably, the first substrate and the second substrate are portions of a single substrate.
According to yet another aspect of the present invention, an SRAM memory cell is provided comprising a substrate assembly having at least one semiconductor layer, and a first semiconductor structure formed within the at least one semiconductor layer with the first semiconductor structure being coupled to a first voltage input. A first pull-up transistor is formed in the first semiconductor structure and comprises a first gate, a first source and a first drain. The first source is coupled to the first semiconductor structure such that the first source is coupled to the first voltage input through parasitic resistance of the semiconductor structure. A first pull-down transistor is formed in the at least one semiconductor layer and comprises a second gate coupled to the first gate, a second source coupled to a second voltage input, and a second drain coupled to the first drain.
The memory cell may further comprise an access transistor formed in the at least one semiconductor layer having one terminal coupled to the first and second drains, another terminal coupled to a column line and an access gate coupled to a row line. Preferably, the at least one semiconductor layer comprises P-type semiconductor material and the semiconductor structure comprises an N-type well
According to a further aspect of the present invention, an SRAM memory cell comprises a substrate assembly having at least one semiconductor layer, and a first semiconductor structure and a second semiconductor structure formed within the at least one semiconductor layer with the first and second semiconductor structures being coupled to a first voltage input. A first pull-up transistor is formed in the first semiconductor structure and comprises a first gate, a first source and a first drain with the first source being coupled to the first semiconductor structure such that the first source is coupled to the first voltage input through parasitic resistance of the first semiconductor structure. A first pull-down transistor is formed in the at least one semiconductor layer and comprises a second gate coupled to the first gate, a second source coupled to a second voltage input, and a second drain coupled to the first drain. A second pull-up transistor is formed in the second semiconductor structure and comprises a third gate, a third source and a third drain with the third source being coupled to the second semiconductor structure such that the third source is coupled to the first voltage input through parasitic resistance of the second semiconductor structure. A second pull-down transistor is formed in the at least one semiconductor layer and comprises a fourth gate coupled to the third gate, a fourth source coupled to the second voltage input, and a fourth drain coupled to the third drain.
Preferably, the at least one semiconductor layer comprises P-type semiconductor material while the first and second semiconductor structures each comprise an N-type well. The first semiconductor structure and the second semiconductor structure may form portions of a single semiconductor structure. The memory cell may further comprise a first access transistor formed in the at least one semiconductor layer having a first terminal coupled to the first and second drains, a second terminal coupled to a first column line and a first access gate coupled to a row line, and a second access transistor formed in the at least one semiconductor layer having a third terminal coupled to the third and fourth drains, a fourth terminal coupled to a second column line and a second access gate coupled to the row line.
According to a still further aspect of the present invention an SRAM memory array is provided comprises a plurality of memory cells arranged in rows and columns. Each of the memory cells comprise a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor and a second access transistor. The first pull-up transistor includes a first substrate, a first source, a first gate coupled to a first node, and a first drain coupled to a second node with the first source being coupled to a first voltage input through parasitic resistance of the first substrate. The first pull-down transistor includes a second drain coupled to the second node, a second gate coupled to the first node, and a second source coupled to a second voltage input. The second pull-up transistor includes a second substrate, a third source, a third gate coupled to the second node, and a third drain coupled to the first node with the third source being coupled to the first voltage input through parasitic resistance of the second substrate. The second pull-down transistor includes a fourth drain coupled to the first node, a fourth gate coupled to the second node, and a fourth source coupled to the second voltage input. The first access transistor includes a first terminal coupled to the first and second drains, a second terminal coupled to a first column line and a first access gate coupled to a row line. The second access transistor includes a third terminal coupled to the third and fourth drains, a fourth terminal coupled to a second column line and a second access gate coupled to the row line. The memory array also includes a memory decoder coupled to the plurality of memory cells for accessing each of the plurality of memory cells via the respective ones of a plurality of the row lines and respective ones of a plurality of the first and second column-lines.
Preferably, the first substrate and the second substrate form portions of a single substrate. The memory array may comprise a plurality of the rows with each of the first and second pull-up transistors making up each of the rows of memory cells sharing a common substrate.
According to yet another aspect of the present invention, an SRAM memory array is provided comprising a plurality of SRAM memory cells arranged in rows and columns and formed on a substrate assembly comprises at least one semiconductor layer. Each of the plurality of memory cells comprise a first semiconductor structure and a second semiconductor structure formed within the at least one semiconductor layer with the first and second semiconductor structures is coupled to a first voltage input. A first pull-up transistor is formed in the first semiconductor structure and comprises a first gate, a first source and a first drain with the first source being coupled to the first semiconductor structure such that the first source is coupled to the first voltage input through parasitic resistance of the first semiconductor structure. A first pull-down transistor is formed in the at least one semiconductor layer and comprises a second gate coupled to the first gate, a second source coupled to a second voltage input, and a second drain coupled to the first drain. A second pull-up transistor is formed in the second semiconductor structure and comprises a third gate, a third source and a third drain with the third source being coupled to the second semiconductor structure such that the third source is coupled to the first voltage input through parasitic resistance of the second semiconductor structure. A second pull-down transistor is formed in the at least one semiconductor layer and comprises a fourth gate coupled to the third gate, a fourth source coupled to the second voltage input, and a fourth drain coupled to the third drain. A first access transistor is formed in the at least one semiconductor layer and includes a first terminal coupled to the first and second drains, a second terminal coupled to a first column line and a first access gate coupled to a row line. A second access transistor is formed in the at least one semiconductor layer and includes a third terminal coupled to the third and fourth drains, a fourth terminal coupled to a second column line and a first access gate coupled to a row line. The memory array includes a memory decoder coupled to the plurality of memory cells for accessing each of the plurality of memory cells via respective ones of a plurality of the row lines and respective ones of a plurality of the first and second column lines.
Preferably, the first substrate and the second substrate form portions of a single substrate. The at least one semiconductor layer may comprise P-type semiconductor material while the first semiconductor structure may comprise an N-type well. The memory array may comprise a plurality of the rows with each of the first and second pull-up transistors making up each of the rows of memory cells sharing the N-type well.
According to yet another aspect of the present invention, a computer system is provided comprising an SRAM memory array and a microprocessor. The memory array comprises a plurality of memory cells arranged in rows and columns with each of the memory cells comprising a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor and a second access transistor. The first pull-up transistor includes a first substrate, a first source, a first gate coupled to a first node, and a first drain coupled to a second node with the first source being coupled to a first voltage input through parasitic resistance of the first substrate. The first pull-down transistor includes a second drain coupled to the second node, a second gate coupled to the first node, and a second source coupled to a second voltage input. The second pull-up transistor includes a second substrate, a third source, a third gate coupled to the second node, and a third drain coupled to the first node with the third source being coupled to the first voltage input through parasitic resistance of the second substrate. The second pull-down transistor includes a fourth drain coupled to the first node, a fourth gate coupled to the second node, and a fourth source coupled to the second voltage input. The first access transistor includes a first terminal coupled to the first and second drains, a second terminal coupled to a first column line and a first access gate coupled to a row line. The second access transistor includes a third terminal coupled to the third and fourth drains, a fourth terminal coupled to a second column line and a second access gate coupled to the row line. The memory array also includes a memory decoder coupled to the plurality of memory cells for accessing each of the plurality of memory cells via the respective ones of a plurality of the row lines and respective ones of a plurality of the first and second column lines. The microprocessor communicates with each of the plurality of memory cells via the memory decoder.
According to a further aspect of the present invention, a computer system is provided comprising a SRAM memory array and a microprocessor. The memory array comprises a plurality of memory cells arranged in rows and columns and formed on a substrate assembly comprises at least one semiconductor layer. Each of the plurality of memory cells comprise a first semiconductor structure and a second semiconductor structure formed within the at least one semiconductor layer with the first and second semiconductor structures is coupled to a first voltage input. A first pull-up transistor is formed in the first semiconductor structure and comprises a first gate, a first source and a first drain with the first source being coupled to the first semiconductor structure such that the first source is coupled to the first voltage input through parasitic resistance of the first semiconductor structure. A first pull-down transistor is formed in the at least one semiconductor layer and comprises a second gate coupled to the first gate, a second source coupled to a second voltage input, and a second drain coupled to the first drain. A second pull-up transistor is formed in the second semiconductor structure and comprises a third gate, a third source and a third drain with the third source being coupled to the second semiconductor structure such that the third source is coupled to the first voltage input through parasitic resistance of the second semiconductor structure. A second pull-down transistor is formed in the at least one semiconductor layer and comprises a fourth gate coupled to the third gate, a fourth source coupled to the second voltage input, and a fourth drain coupled to the third drain. A first access transistor is formed in the at least one semiconductor layer and includes a first terminal coupled to the first and second drains, a second terminal coupled to a first column line and a first access gate coupled to a row line. A second access transistor is formed in the at least one semiconductor layer and includes a third terminal coupled to the third and fourth drains, a fourth terminal coupled to a second column line and a first access gate coupled to a row line. The memory array includes a memory decoder coupled to the plurality of memory cells for accessing each of the plurality of memory cells via respective ones of a plurality of the row lines and respective ones of a plurality of the first and second column lines. The microprocessor communicates with each of the plurality of memory cells via the memory decoder.
According to a still further aspect of the present invention, a method of fabricating an SRAM memory cell is provided. A substrate assembly having at least one semiconductor layer is provided. A first semiconductor structure is formed within the at least one semiconductor layer. A first source and a first drain of a first pull-up transistor are formed in the first semiconductor structure. A second source and a second drain of a first pull-down transistor are formed in the at least one semiconductor layer. A first contact and a second contact are formed within the first semiconductor structure. A first gate for the first pull-up transistor and a second gate for the first pull-down transistor are formed. The first drain is coupled to the second drain and the first gate is coupled to the second gate. The first source is coupled to one of the first and second contacts such that with the other of the first and second contacts coupled to a first voltage input the first source is coupled to the first voltage input through parasitic resistance of the first semiconductor structure.
According to another aspect of the present invention, a method of fabricating an SRAM memory cell is provided. A substrate assembly having at least one semiconductor layer is provided. A first semiconductor structure and a second semiconductor structure are formed within the at least one semiconductor layer. A first source and a first drain of a first pull-up transistor are formed in the first semiconductor structure. A second source and a second drain of a first pull-down transistor are formed in the at least one semiconductor layer. A third source and a third drain of a second pull-up transistor are formed in the second semiconductor structure. A fourth source and a fourth drain of a second pull-down transistor are formed in the at least one semiconductor layer. A first contact and a second contact are formed within the first semiconductor structure. A third contact and fourth contact are formed within the second semiconductor structure. A first gate for the first pull-up transistor, a second gate for the first pull-down transistor, a third gate for the second pull-up transistor and a fourth gate for the second pull-down transistor are formed. The first drain is coupled to the second drain and the third drain is coupled to the fourth drain. The first gate is coupled to the second gate and the third gate is coupled to the fourth gate. The first source is coupled to one of the first and second contacts such that with the other of the first and second contacts coupled to a first voltage input the first source is coupled to the first voltage input through parasitic resistance of the first semiconductor structure. The third source is coupled to one of the third and fourth contacts such that with the other of the third and fourth contacts coupled to the first voltage input the third source is coupled to the first voltage input through parasitic resistance of the second semiconductor structure.
Preferably, the first substrate and the second substrate form portions of a single substrate. The at least one semiconductor layer may comprise P-type semiconductor material while the first semiconductor structure may comprise an N-type well.
According to yet another aspect of the present invention, a method of fabricating an SRAM memory array is provided. A substrate assembly having at least one semiconductor layer is provided. A plurality of memory cells arranged in rows and columns are formed. Each of the plurality of memory cells are fabricated according to the following steps. A first semiconductor structure is formed within the at least one semiconductor layer. A second semiconductor structure is formed within the at least one semiconductor layer. A first source and a first drain of a first pull-up transistor are formed in the first semiconductor structure. A second source and a second drain of a first pull-down transistor are formed in the at least one semiconductor layer. A third source and a third drain of a second pull-up transistor are formed in the second semiconductor structure. A fourth source and a fourth drain of a second pull-down *transistor are formed in the at least one semiconductor layer. A first terminal and a second terminal of a first access transistor are formed in the at least one semiconductor layer. A third terminal and a fourth terminal of a second access transistor are formed in the at least one semiconductor layer. A first contact and a second contact are formed within the first semiconductor structure. A third contact and fourth contact are formed within the second semiconductor structure. A first gate for the first pull-up transistor, a second gate for the first pull-down transistor, a third gate for the second pull-up transistor, a fourth gate for the second pull-down transistor, a first access gate for the first access transistor, and a second access gate for the second access transistor are formed. The first drain is coupled to the second drain and the third drain is coupled to the fourth drain. The first gate is coupled to the second gate and the third gate is coupled to the fourth gate. The first terminal is coupled to the first and second drains and the third terminal is coupled to the third and fourth drains. The first source is coupled to one of the first and second contacts such that with the other of the first and second contacts coupled to a first voltage input the first source is coupled to the first voltage input through parasitic resistance of the first semiconductor structure. The third source is coupled to one of the third and fourth contacts such that with the other of the third and fourth contacts coupled to the first voltage input the third source is coupled to the first voltage input through parasitic resistance of the second semiconductor structure. The first and second access gates of each of the plurality of memory cells are coupled to respective row lines. The second terminals of each of the plurality of memory cells are coupled to respective first column lines. The fourth terminals of each of the plurality of memory cells are coupled to respective second column lines.
Preferably, the first substrate and the second substrate form portions of a single substrate. Each of the first and second pull-up transistors making up each of the rows of memory cells may share the N-type well.
According to a still further aspect of the present invention, a method of fabricating a computer system is provided. A memory array and a microprocessor are provided. The memory array comprises a plurality of memory cells arranged in rows and columns and formed on a substrate assembly comprising at least one semiconductor layer. Each of the plurality of memory cells comprise a first semiconductor structure and a second semiconductor structure formed within the at least one semiconductor layer with the first and second semiconductor structures is coupled to a first voltage input. A first pull-up transistor is formed in the first semiconductor structure and comprises a first gate, a first source and a first drain with the first source being coupled to the first semiconductor structure such that the first source is coupled to the first voltage input through parasitic resistance of the first semiconductor structure. A first pull-down transistor is formed in the at least one semiconductor layer and comprises a second gate coupled to the first gate, a second source coupled to a second voltage input, and a second drain coupled to the first drain. A second pull-up transistor is formed in the second semiconductor structure and comprises a third gate, a third source and a third drain with the third source being coupled to the second semiconductor structure such that the third source is coupled to the first voltage input through parasitic resistance of the second semiconductor structure. A second pull-down transistor is formed in the at least one semiconductor layer and comprises a fourth gate coupled to the third gate, a fourth source coupled to the second voltage input, and a fourth drain coupled to the third drain. A first access transistor is formed in the at least one semiconductor layer and includes a first terminal coupled to the first and second drains, a second terminal coupled to a first column line and a first access gate coupled to a row line. A second access transistor is formed in the at least one semiconductor layer and includes a third terminal coupled to the third and fourth drains, a fourth terminal coupled to a second column line and a first access gate coupled to a row line. The memory array includes a memory decoder coupled to the plurality of memory cells for accessing each of the plurality of memory cells via respective ones of a plurality of the row lines and respective ones of a plurality of the first and second column lines. The microprocessor communicates with each of the plurality of memory cells via the memory decoder.